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The IEEE 1164 standard defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description. It was sponsored by the Design Automation Standards Committee of the Institute of Electrical and Electronics Engineers (IEEE). The standardization effort was based on the donation of the Synopsys MVL-9 type declaration. The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in the following order: This system promoted a useful set of logic values that typical CMOS logic designs could implement in the vast majority of modeling situations. The 'Z' literal makes tri-state buffer logic easy. The 'H' and 'L' weak drives permit wired-AND and wired-OR logic. Additionally, the 'U' state is the default value for all object declarations so that during simulations uninitialized values are easily detectable and thus easily corrected if necessary. In VHDL, the hardware designer makes the declarations visible via the following library and use statements:library IEEE; use IEEE.std_logic_1164.all; ==See also== *Four valued logic *IEEE 1364 defines a four-valued logic (among other things) 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「IEEE 1164」の詳細全文を読む スポンサード リンク
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